The demand for new high performance speeds and features in high-speed serial data communication is ever increasing. One common high-speed serial interface (HSSI) protocol used to achieve such speeds is PCI Express (PCIe), which is a low-cost, scalable, switched, point-to-point, serial I/O interconnection scheme. PCIe provides a number of benefits over existing standards, including increased bandwidth availability and support for real-time data transfer services.
The PCIe standard defines link power management states such as L0s, L1, and L2/L3 that a PCIe physical Link is permitted to enter in response to either software drive “D-state” or active state power management activities. These link power management states allow PCIe devices to save power when the PCIe link is idle. Description of these states can be found in the “PCI Express Base Specification,” Revision 3.0, dated Nov. 10, 2010, which is hereby incorporated by reference in its entirety.
Although the PCIe link power management is well-defined, few systems with PCIe interconnect fully utilize the benefits of the PCIe low power states. One example of such devices that typically do not fully utilize the benefits of PCIe link power management is FPGA devices.
The efficiency of the power management of a system architecture depends on how much of the device circuitry is gated during the PCIe low power states. This dependency of gating efficiency on the amount of gated circuitry is exemplified in devices with hard-coded intellectual property (IP) blocks that support PCIe functionality. Where the hard IP does not fully utilize the PCIe low power states to achieve idle power savings, the power consumption may significantly increase. This increase in power consumption may occur not only in the hard IP but also in circuitry associated with communication layers, such as physical coding sublayer (PCS) and physical medium attachment (PMA).
As demand for higher data rates and more functionality continues to grow, so too does the demand for power, in order to fulfill ever-increasing performance and throughput requirements. As such, power optimization, power consumption reduction, and intelligent power management are becoming increasingly more important.